Digital Design Engineer
The Swatch Group Ltd
2074 Marin
vor 20 Std.

Job description

To strengthen the team, our Smart Systems Business Unit is currently looking for a digital design engineer. You will have the opportunity to work from specification and system level study to design implementation and verification on true ultra-

low power design in close collaboration with customer and production support team. We are looking for an experienced professional, motivated to drive design, methodology and best practices with a direct effect on product performance and BU bottom line.

Primary responsibilities :

  • Work with analog team on product specifications and system architecture.
  • Perform state-of-the-art ultra-low power digital design implementation.
  • Digital IP verification using UVM methodology. Drive verification subcontractors when relevant.
  • Contribute to top level verification with analog modelling to verify system usecase and testmodes.
  • Drive or contribute to synthesis and physical implementation.
  • Generate industrial test patterns.
  • Improve validation methods and strategy to cut down product time to market while maintaining strong validation quality.
  • Collaborate with others sites in US and Prague and others Business Units to improve synergy on methodology and share best practices.
  • Contribute to product qualification together with analog designers and test engineers.
  • Profile

  • MSc or BSc degree in electronics / microelectronics.
  • 5-10 years working experience in a semiconductor environment.
  • Templayer, flexible, hard worker, analytical.
  • Likes to work in multicultural environment.
  • Creative, accountable, goal-oriented and efficient.
  • Professional requirements

  • A strong candidate has several years of digital design experience on RF or mixed signal products and he is eager to participate to all steps of product development, from definition to ramp up.
  • Front-end digital design experience (system, architecture, RTL design, verification) in mixed signal environment.
  • UVM verification methodology is a clear advantage.
  • Physical implementation (synthesis, P&R, STA) is a plus, as well as experience in analog modelling.
  • Strong understanding of wireless systems and communication protocols (experience in RFID would be a plus).
  • Knowledge of microntroller architecture and integration into a SOC.
  • UVM verification and / or analog modelling experience would be an asset.
  • Languages

  • English written and verbal is a must, French would be a great advantage
  • Any other language is welcome
  • Company address

    EM Microelectronic-Marin Ltd

    CH-2074 Marin-Epagnier

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